CMOS-Compatible Silicon-on-Insulator MESFETs for Extreme Environments

Authored by: Trevor J. Thornton , William Lepkowski , Seth J. Wilk , Mohammad Reza Ghajar , Asha Balijepalli , Joseph Ervin

Extreme Environment Electronics

Print publication date:  November  2012
Online publication date:  November  2012

Print ISBN: 9781439874301
eBook ISBN: 9781439874318
Adobe ISBN:

10.1201/b13001-28

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Abstract

Metal–semiconductor field-effect transistors (MESFETs) have long been studied for their extreme environment applications, with the most widely developed technologies making use of compound semiconductor materials such as GaAs, and more recently GaN and SiC [1]. These technologies are, however, expensive and suffer from relatively low integration levels compared to ULSI CMOS. On the other hand, a CMOS-compatible MESFET would enable the manufacturing of integrated circuits for extreme environment applications using low-cost, high-volume CMOS foundries. Silicon-based MESFETs have been demonstrated using conventional bulk substrates [25], as well as silicon-on-sapphire (SOS) [4,6,7] and silicon-on-insulator (SOI) wafers [7,811]. For any silicon-based approach to be widely adopted, it is important that the MESFETs can be manufactured alongside the MOSFETs with no changes to the CMOS process flow. This chapter describes one such approach [12] based on SOI and SOS CMOS technologies that has been demonstrated at a variety of different foundry services. In Section 23.2, the MESFET architecture is presented along with a description of the CMOS-compatible process flow. This is followed by a summary of the DC and RF device characteristics in Section 23.3 and a description of the Spice model extraction in Section 23.4. Measurements of the device performance in hostile environments including high radiation doses (TID = 300 krad) and large voltage swings (VDD > 50 V) are presented in Sections 23.5 and 23.6, respectively. By way of conclusion, Section 23.7 discusses the performance enhancement expected for silicon MESFETs fabricated using highly scaled CMOS technologies and introduces an alternative MESFET architecture that is compatible with the ultrathin silicon layers described in the ITRS roadmap for fully depleted (FD) SOI CMOS.

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