Using Temperature to Explore the Scaling Limits of SiGe HBTs

Authored by: Jiahui Yuan

Extreme Environment Electronics

Print publication date:  November  2012
Online publication date:  November  2012

Print ISBN: 9781439874301
eBook ISBN: 9781439874318
Adobe ISBN:

10.1201/b13001-24

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Abstract

The goal of achieving terahertz (THz) speeds using silicon-based transistors has generated significant recent interest. In this chapter, we use operating temperature to explore the performance limits of SiGe HBTs. Different approaches for vertical profile scaling and parasitics reductions are investigated. Record peak fT (current-gain cutoff frequency), fmax (maximum oscillation frequency), fT × BVCEO (open-base collector–emitter breakdown voltage), and τgate (ring oscillator gate delay) were achieved at cryogenic temperatures using modest lithography. These remarkable levels of performance demonstrate the capabilities of a silicon-based transistor reaching half-THz frequency response. The consequences of cooling SiGe HBTs are in many ways similar to that of combined vertical and lateral device scaling. The associated device physics observed at cryogenic temperatures in these devices provide important insights into further device scaling for THz speeds at room temperature. A new scaling roadmap predicts that fT and fmax of room-temperature SiGe HBTs could potentially achieve 800 and 900 GHz with a BVCEO of 1.1 V at 32 nm lithography node. The experimental work and some discussions presented in this chapter can also be found in Refs. [17].

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