Abstract

There is a widespread and intense research interest in the fabrication, characterization, and manipulation of semiconductor nanowires (Duan and Lieber 2000, Duan et al. 2000, Lee et al. 2001, Zhang et al. 2001, Bjork et al. 2002), with the aim to develop the novel “bottom up” approach to microelectronic circuit fabrication. In this approach, nanodevices and nanocircuits are assembled from the bottom up, using nano-size building blocks, such as carbon nanotubes (Rao et al. 1997, 2003, Tans et al. 1998, Liang et al. 2001) or semiconductor nanowires. This is a paradigm shift from the traditional “top down” approach, in which nano-size devices are etched into a bulk material using lithographic techniques (Kalliakos et al. 2007, Perez-Martinez et al. 2007). As it is now easy to produce nano-building blocks in large numbers with relatively inexpensive equipment, current research focus is also on developing techniques for manipulating the nano-building blocks (Whang et al. 2003a,b, Pauzauskie et al. 2006, Jamshidi et al. 2008), novel device structures (Cui and Lieber 2001, Duan et al. 2001, Huang et al. 2001b), and circuit architectures (Dehon 2003, Dehon et al. 2003, Zhong et al. 2003) that suit the “bottom up” approach.