Chip-Level Communication Services

Authored by: M. Grammatikakis , H. Ahmadian , M. Coppola , S. Kavvadias , A. Mouzakitis , K. Papadimitriou , A. Papagrigoriou , P. Petrakis , V. Piperaki , M. Soulié , G. Tsamis

Distributed Real-Time Architecture for Mixed-Criticality Systems

Print publication date:  August  2018
Online publication date:  September  2018

Print ISBN: 9780815360643
eBook ISBN: 9781351117821
Adobe ISBN:

10.1201/9781351117821-7

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Abstract

This chapter elaborates on chip-level solutions in mixed-criticality systems, which are categorized in memory and network bandwidth regulations, address interleaving and support for mixedcriticality at the Network On Chip (NoC) level. In Section 7.1, MemGuardXt and NetGuardXt are introduced as memory and network bandwidth management policies to improve communication intensive memory-bound applications. Section 7.2 elaborates on the architecture and evaluation of the hardware MemGuard and in Section 7.3 address interleaving at the NoC-level is discussed. In Section 7.4, requirements, architecture and operational specification of the time-triggered extension layer at on-chip Network Interface (NI) are described. This hardware building block serves as an extension to STMicroelectronics NoC (STNoC) to support heterogeneous types of communication in mixed-criticality systems.

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