Simulation of Single-Event Effects on Fully Depleted Silicon-on-Insulator (FDSOI) CMOS

Authored by: Walter Calienes , Bartra Andreas Vladimirescu , Ricardo Reis

Semiconductor Devices in Harsh Conditions

Print publication date:  November  2016
Online publication date:  November  2016

Print ISBN: 9781498743808
eBook ISBN: 9781315368948
Adobe ISBN:

10.1201/9781315368948-4

 

Abstract

The continuous scaling of transistors is allowing an increase in the number of components on a chip and also a reduction of voltage values defining a ‘logical’ one. This voltage reduction also makes the circuits more sensitive to radiation effects, as the needed charge to cause a bit to flip is reduced. This chapter presents simulations of single-event effects in fully depleted silicon-on-insulator (FDSOI) transistors and static random access memory (SRAM) cells, comparing these effects with the ones in a traditional bulk complementary metal oxide semiconductor (CMOS) technology. A comparison of resilience with heavy-ion impacts on the drain region between a 32 nm bulk CMOS transistor, a 28 nm FDSOI transistor and a 28 nm high-K FDSOI transistor is presented. The impacts were performed in different transistor locations at different impact angles, whereas previous works considered the impact just at a 0° angle. This comparison was performed with the device in the off state using two-dimensional (2D) technology computer-aided design (TCAD) simulations.

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Simulation of Single-Event Effects on Fully Depleted Silicon-on-Insulator (FDSOI) CMOS

3.1  Introduction

The continuous scaling of transistors is allowing an increase in the number of components on a chip and also a reduction of voltage values defining a ‘logical’ one. This voltage reduction also makes the circuits more sensitive to radiation effects, as the needed charge to cause a bit to flip is reduced. This chapter presents simulations of single-event effects in fully depleted silicon-on-insulator (FDSOI) transistors and static random access memory (SRAM) cells, comparing these effects with the ones in a traditional bulk complementary metal oxide semiconductor (CMOS) technology. A comparison of resilience with heavy-ion impacts on the drain region between a 32 nm bulk CMOS transistor, a 28 nm FDSOI transistor and a 28 nm high-K FDSOI transistor is presented. The impacts were performed in different transistor locations at different impact angles, whereas previous works considered the impact just at a 0° angle. This comparison was performed with the device in the off state using two-dimensional (2D) technology computer-aided design (TCAD) simulations.

3.2  Fundamentals of the Single-Event Effects

Space and ground environments are reached by a lot of particles created by solar, cosmic or terrestrial activities. These particles can be charged particles (such as electrons, protons or heavy ions) or electromagnetic radiation (such as X-ray and gamma photons). When one of these particles funnels through the silicon die, it loses energy due to an electron–hole pair production. Protons and neutrons can be produced by nuclear reactions, and they can ionise silicon in a similar manner. The particle ionises the silicon in its track, as shown in Figure 3.1. In summary, the basic transient mechanism due to a particle impact can be described in three steps: (1) charge deposition, (2) charge transport and (3) charge collection (Munteanu and Autran, 2008). These phenomena are due to the photocurrents generated in silicon when it is hit by particles or radiation (Calienes and Reis, 2011).

The charges created by particle impact vary with the type of the particle, the hit angle θ and the impact location (Messenger, 1982). These charges produce an additional transient current Ip(t) and an abnormal charge Qp in the silicon structure. The model of this transient is summarised in the follow equations:

Alpha-particle with kinetic energy E

Figure 3.1   Alpha-particle with kinetic energy Ekα impacts an inverse-biased n-p silicon junction with angle θ. The dotted line represents a metallurgic junction electric field.

Transient current simulation. The total CC in this case is 31.5 fC. (From Calienes, W., and Reis, R., SET and SEU simulation toolkit for LabVIEW, presented at Proceedings of European Conference on Radiation and Its Effects on Components and Systems [RADECS], Seville, Spain, September 19, 2011.)

Figure 3.2   Transient current simulation. The total CC in this case is 31.5 fC. (From Calienes, W., and Reis, R., SET and SEU simulation toolkit for LabVIEW, presented at Proceedings of European Conference on Radiation and Its Effects on Components and Systems [RADECS], Seville, Spain, September 19, 2011.)

3.1 I p ( t ) = I 0 ( exp ( t / τ F ) exp ( t / τ R ) )
3.2 Q p = I 0 ( τ F τ R )

where I0 is the maximum current due the generated charges, τR is the collection time constant of the junction and τF is the time constant to establish the ion track. Figure 3.2 presents an example of transient current simulation using Equation 3.1, with I0 = 350 μA, τR = 10 ps and τF = 100 ps. The transient current Ip(t) is maximum when t = (τF τR ln(τRF))/(τR − τF). The terms in Equation 3.1 can be expressed in the following forms (Messenger, 1982):

3.3 I 0 = q μ N E 0 sec ( θ )
3.4 τ F = [ μ dE ( X ) / dX ] 1

where q = 1.602 × 10−19 C is the electron charge, μ is the average mobility (which depends on the electric field E[X]), N is the electron–hole pair linear density (cm−1), E0 = E(0) is the electric field at X = 0, and dE(X)/dX is the change rate of the electric field with respect to the position. The electron–hole pair linear density depends on the absolute linear energy transfer (LET) in units of megaelectronvolts per centimetre (Holbert, 2012):

3.5 N = LET / E gSi

where EgSi = 3.6 eV is the necessary energy to create an electron–hole pair in silicon. LET depends on the particle kinetic energy E. The relative LET for a material in MeV-cm2/mg for a particle is defined as

3.6 LET M = LET / ρ M

where ρM is the material volumetric density. In silicon, ρM = ρSi = 2329 mg/cm3. The relative silicon LET is also expressed in other units as picocoulombs per micrometre (1 pC/μm = 96.525 MeV-cm2/mg) (Naseer, 2008).

Table 3.1 shows the principal sources of natural space radiation (Ecoffet, 2007). These radiations can reach the earth. Other radiation sources include the manufacturing materials used in the fabrication of integrated circuits (Wrobel et al., 2009).

In the literature, the faults due to particle impacts are known as single-event effects because they are due to a single particle or heavy ion. The single-event effects have subcategories (Boudenot, 2007), such as

  • Single-event transient (SET): Transient fault in combinational circuits
  • Single-event upset (SEU): Transient fault in sequential circuits and memories

    Table 3.1   Main Sources of Natural Space Radiation

    Radiation beltsElectrons1 eV to 10 MeV
     Protons1 keV to 500 MeV
    Solar flaresProtons1 keV to 500 MeV
     Ions1 to few 10 MeV/n
    Galactic cosmic raysProtons and ionsMax flux at about 300 MeV/n

    Source: Ecoffet, F., in Velazco, R., et al. (Eds.), Radiations Effects on Embedded Systems, Springer, Berlin, 2007, pp. 31–68.

  • Single-event latch-up (SEL): Destructive fault; can affect the CMOS structure
  • Single-event burnout (SEB): Destructive fault; affects power metal oxide semiconductor field-effect transistors (MOSFETs)
  • Single-event gate rupture (SEGR): Fault that can damage the submicron structure
  • Single hard error (SHE): Destructive fault in complex circuits

SET and SEU are the only transient faults. SEU is a failure that changes the value of a bit in a register or memory cell. A register with a logical value 1 is changed to a logical 0 after being affected or vice versa. SEU failures are also known as soft errors. Since the SET affects the functionality of transistors, creating an anomalous current, it can affect the final result of a logic operation. These transient faults can introduce a temporary error, so they will not affect future circuit operation.

3.3  CMOS Bulk and FDSOI Devices

The traditional industry standard, the MOSFET bulk technology, is facing problems with static power consumption and other second-order effects, in technology nodes below 130 nm. To try to handle these problems, one can explore new materials to replace silicon, such as hybrids like Ge-Si or gallium-arsenide, or try to replace the gate silicon oxide by other types of insulating materials to keep up with Moore’s law. Other devices are being developed in 3D, such as Fin-FETs, to keep increasing transistor density.

A set of structures was designed using TCAD simulation tools. Figure 3.3a shows a 32 nm predictive technology model (PTM) n-type MOSFET (NMOS) bulk transistor. This transistor has a p-type substrate doping of 4.12 × 1018 cm−3, a junction depth of 50 nm, a silicon oxide thickness tox of 1.3 nm and a metal-gate work function ΦM of 4.25 eV. Figure 3.3b presents a 28 nm FDSOI high-K NMOS transistor. This transistor is a p-type one, and it has a substrate doping of 1 × 1014 cm−3, a p-type channel doping of 1 × 1015 cm−3 with a thickness of 8.5 nm, an equivalent gate oxide thickness tEOX of 0.75 nm (SiO2 thickness of 0.55 nm and HfO2 thickness of 1.283 nm), a buried oxide (BOX) thickness of 20 nm, a p-type back plane (BP) doping of 2 × 1018 cm−3 with a thickness of 25 nm and a metal-gate work function ΦM of 4.52 eV. Another 28 nm FDSOI transistor was also created with a 0.9 nm silicon oxide thickness, with the same characteristics and metal-gate work function as the 28 nm FDSOI high-K, to compare other geometry effects. Figure 3.4 shows a comparison between the Id and Vg curves of these devices using the TCAD-created structures and the corresponding SPICE model card. For both devices, the width is Wg = 300 nm. Table 3.2 presents the characteristics of these devices under test.

Devices designed using TCAD tools. (a) 32 nm NMOS bulk. (b) 28 nm NMOS FDSOI.

Figure 3.3   Devices designed using TCAD tools. (a) 32 nm NMOS bulk. (b) 28 nm NMOS FDSOI.

3.4  Heavy-Ion Impact Simulation on Single Devices

In this case, the simulations were performed with the presented devices in the off state, such as shown in Figure 3.5a and b. Figure 3.5a presents a 32 nm bulk CMOS transistor setup, and Figure 3.5b shows a 28 nm FDSOI setup, where the BP terminal is grounded. In both cases, each device is biased with 1 V on the drain terminal. The device widths are Wg = 100 nm for both.

The heavy ion for the simulation was configured with LET = 100 MeV-cm2/mg (or 1.0447 pC/μm), a total track range l = 300 nm and a characteristic distance wt = 20 nm. The total simulation time was Ts = 100 ps, and the heavy ion impacted at ti = 25 ps (Calienes et al., 2015).

The simulated heavy ion impacted the raised terminals at six different angles θ (0°, 15°, 30°, 45°, 60° and 75°) and at five different locations Li (measured in nanometres from transistor spacers: 6, 12, 18, 24 and 30 nm) for each angle; that means 30 simulations. Figure 3.5c presents how the heavy-ion impact is performed using the distance Li and impact angle θ.

I

Figure 3.4   Id vs. Vg calibration curves between SPICE and TCAD for 32 nm bulk, 28 nm FDSOI and 28 nm FDSOI high-K (Wg = 300 nm).

Table 3.2   Electrical Characteristics of the Studied Devices

Parameter Name

32 nm Bulk

28 nm FDSOI High-K

28 nm FDSOI

Turn-on current (Ion)

778 μA/μm

727 μA/μm

702 μA/μm

Turn-off current (Ioff)

423 pA/μm

421 pA/μm

461 pA/μm

Saturation threshold voltage (Vth,SAT)

229 mV

219 mV

218 mV

Linear threshold voltage (Vth,LIN)

300 mV

252 mV

254 mV

Drain-induced Barrier Lowering (DIBL)

81 mV/V

38 mV/V

41 mV/V

Subthreshold slope (SS)

78 mV/dec

75 mV/dec

75 mV/dec

The heavy-ion impacts on the drain and source terminals produce a transient current. To obtain the collected charge (CC) after the ion hit, it is necessary to integrate the transient current with respect to time for each Li-θ pair (Calienes et al., 2015).

Simulation setup. (a) 32 nm bulk. (b) 28 nm FDSOI. (c) Heavy-ion impact setup. The “ø” symbol is part of circuits scheme in (a) and (b).

Figure 3.5   Simulation setup. (a) 32 nm bulk. (b) 28 nm FDSOI. (c) Heavy-ion impact setup. The “ø” symbol is part of circuits scheme in (a) and (b).

3.4.1  Bulk Transistor of 32 nm

3.4.1.1  Heavy-Ion Impacts the Drain Terminal

The heavy ion with LET = 100 MeV-cm2/mg was impacted on the raised drain terminal of the 32 nm bulk transistor using the circuit configuration presented in Figure 3.5a, and the resulting CC is presented in Figure 3.6. The heavy ion produces a maximum CC of 32.29 fC when Li = 30 nm and θ = 30°. The minimum CC is 13.12 fC when Li = 6 nm and θ = 75°. The tendency in these conditions is for CC to decrease when the impact is near to the nitride spacer and the angle is increased.

Total CC results of 100 MeV-cm

Figure 3.6   Total CC results of 100 MeV-cm2/mg heavy-ion impact on 32 nm bulk transistor drain terminal (ΦM = 4.25 eV, Wg = 100 nm). (From Calienes et al., 2015.)

When the Li value is increased, CC tends to stay constant, with little charge variation; for example, with θ = 45°, CC is 27.27 fC for Li = 6 nm, 30.80 fC for Li = 18 nm and 31.27 fC for Li = 30 nm. When θ = 15°, CC is even more constant.

When the impact angle θ is increased, the CC variation presents a ‘sinusoidal’ behaviour in all impact locations Li; that is, CC is low at θ = 0°, higher at θ = 30° and at θ = 75° is lower than the charge at θ = 0°, as Figure 3.6 presents.

3.4.1.2  Heavy-Ion Impacts the Source Terminal

When the heavy ion impacted the source terminal of a 32 nm bulk transistor in the off state, the CC was less than the drain terminal impact case. Figure 3.7 shows this CC behaviour. The ion produces a maximum CC of 29.89 fC when Li = 12 nm and θ = 60°, and the minimum CC is 2.31 fC when Li = 30 nm and θ = 0°.

When Li is increased, the CC tends to decrease slowly, almost constantly; for example, when θ = 30°, for Li = 6 nm the CC is 18.04 fC, for Li = 18 nm it is 15.45 fC and for Li = 30 nm it is 12.99 fC, as Figure 3.7 shows.

In the case of an increase in θ, the CC increases up to θ = 60°, and then it declines slightly when θ > 60°; for example, when Li = 24 nm, for θ = 0° the CC is 3.83 fC, for θ = 30° it is 14.24 fC, for θ = 60° it is 27.49 fC and for θ = 75° it is 22.25 fC.

Total CC results of 100 MeV-cm

Figure 3.7   Total CC results of 100 MeV-cm2/mg heavy-ion impact on 32 nm bulk transistor source terminal (ΦM = 4.25 eV, Wg = 100 nm).

3.4.2  High-K FDSOI Transistor of 28 nm

3.4.2.1  Heavy-Ion Impacts the Drain Terminal

In this case, the 100 MeV-cm2/mg heavy ion impacted the 28 nm high-K FDSOI drain terminal. The simulation was conducted in the same way as the simulation of the bulk transistor. Figure 3.8 shows the CC as a function of Li and θ°. In this case, 5.13 fC is the maximum CC and it occurs when Li = 24 nm and θ = 75°. The minimum CC is 0.45 fC when Li = 30 nm and θ = 0°, a vertical impact far from the nitride spacer.

When Li is increased, the CC tends to decrease; for example, for θ = 45°, at Li = 6 nm the charge is 2.78 fC, at Li = 18 nm it is 2.23 fC and at Li = 30 nm it is 1.31 fC. There are several exceptions at θ = 30° and θ = 60°, but in general, the trend is met. If θ increases, the CC also increases. The minimum CC is when θ = 0° and the maximum when θ = 75°, regardless of the impact location Li.

3.4.2.2  Heavy-Ion Impacts the Source Terminal

When the 100 MeV-cm2/mg heavy-ion impacts the 28 nm high-K FDSOI source terminal, the maximum CC value is 4.46 fC at Li = 6 nm and θ = 75°, very close to the nitride spacer, and the minimum is 0.096 fC at Li = 30 nm and θ = 0°, far from the nitride spacer. Figure 3.9 presents these CC tendencies in function of Li and θ°.

Total CC results of 100 MeV-cm

Figure 3.8   Total CC results of 100 MeV-cm2/mg heavy-ion impact on 28 nm high-K FDSOI transistor drain terminal (ΦM = 4.52 eV, Wg = 100 nm).

Total CC results of 100 MeV-cm

Figure 3.9   Total CC results of 100 MeV-cm2/mg heavy-ion impact on 28 nm high-K FDSOI transistor source terminal (ΦM = 4.52 eV, Wg = 100 nm).

When Li increases, the CC tends to decrease slowly; for example, for θ = 30°, at Li = 6 nm the CC is 0.38 fC, at Li = 18 nm it is 0.24 fC and at Li = 30 nm it is 0.15 fC. The exception is at θ = 75°, when the CC variation in function of Li is greater than at other impact angles. When θ is increased, the CC tends to increase in all cases. Regardless of the Li value, the maximum CC occurs when θ = 75°, and the minimum when θ = 0°.

3.4.3  FDSOI Transistor of 28 nm

3.4.3.1  Heavy-Ion Impacts the Drain Terminal

The 100 MeV-cm2/mg heavy-ion impact on the 28 nm FDSOI drain terminal was performed in the same way as in the previous simulations. Figure 3.10 presents the result of the TCAD simulation for this case. The maximum CC is 4.20 fC and occurs when Li = 12 nm and θ = 75°, close to the drain nitride spacer. The minimum CC for this case is 0.41 fC at Li = 30 nm and θ = 0°, vertical and far from the spacer.

When Li increases, the CC tends to decrease; for example, for θ = 60°, at Li = 6 nm the CC is 3.69 fC, at Li = 18 nm the charge is 3.50 fC and at Li = 30 nm it is 2.42 fC. The exception is when the impact occurs with θ = 75°. In this case, the charge increases slowly from 3.58 fC at Li = 18 nm to 3.74 fC at Li = 30 nm. When the angle θ increases, the CC also increases in all cases. The minimum CC values occur at θ = 0° and the maximum values occur when θ = 75°, regardless of the impact location Li.

Total CC results of 100 MeV-cm

Figure 3.10   Total CC results of 100 MeV-cm2/mg heavy-ion impact on 28 nm FDSOI transistor drain terminal (ΦM = 4.52 eV, Wg = 100 nm).

3.4.3.2  Heavy-Ion Impacts the Source Terminal

For the 28 nm FDSOI source terminal impact case, the maximum CC is 4.10 fC when Li = 6 nm and θ = 75°, and the minimum charge is 0.0706 fC at Li = 30 nm and θ = 0°. The CC behavior in this case is similar to the one with a drain impact, but in this case the CC is much lower. These results are shown in Figure 3.11.

3.4.4  Conclusions Related to Heavy-Ion Impact Simulation on Single Devices in Different Technologies

The collected transient charge and drain current peak depend on the substrate bias, lightly doped drain (LDD) geometry, silicon volume in the body/channel region, gate equivalent oxide thickness and polymeric metal-gate materials (Calienes et al., 2015). The generated charge due to an ion impact is collected by recombination, drift and diffusion processes. The transient peak current depends directly on the drift current component and substrate bias.

Total CC results of 100 MeV-cm

Figure 3.11   Total CC results of 100 MeV-cm2/mg heavy-ion impact on 28 nm FDSOI transistor source terminal (ΦM = 4.52 eV, Wg = 100 nm).

The quantity of CC is directly proportional to the silicon volume, and it also depends on the doping of the body (Calienes et al., 2015). In the ultrathin body and box (UTBB) FDSOI case, the silicon body thickness is less than the channel length and limited by the BOX. The recombination is lower than in the bulk transistor case, because the FDSOI silicon body is much thinner than in the bulk one. In the worst case, the CC in the FDSOI simulated transistors is smaller by a factor of approximately 7.68 than the worst-case CC in a bulk transistor. The electron density in the device is a measure of how the heavy-ion impact affects a device. Figures 3.12 through 3.14 show the variation over time of the electron density for each simulated device in the worst CC cases when a 100 MeV-cm2/mg heavy-ion impacts the drain terminal.

The most sensitive device area is the reverse-biased drain and source n-p junction (Messenger, 1982). In a bulk device, the maximum CC occurs when Li = 30 nm and θ = 30°, when the ion track funnels through the LDD around the drain region, as shown in Figure 3.15a. A similar phenomenon occurs with a FDSOI device when Li = 12 nm and θ = 75°, as in Figure 3.15b. In the high-K FDSOI case, this maximum CC occurs when Li = 24 nm and θ = 75°. The CC difference between FDSOI and high-K FDSOI is small: 0.93 fC. In all cases, the ion funnels through the LDD and produces a maximum CC. Also, the LDD doping in the bulk transistor is –8 × 1017cm−3 and the LDD doping in both FDSOI transistors is approximately –2 × 1014 cm−3. The silicon doping in the body also has influence on the CC.

Electron density over time in 32 nm bulk transistor when Li = 30 nm and θ = 30° (Φ

Figure 3.12   Electron density over time in 32 nm bulk transistor when Li = 30 nm and θ = 30° (ΦM = 4.25 eV, Wg = 100 nm).

Electron density over time in 28 nm FDSOI transistor when Li = 12 nm and θ = 75° (Φ

Figure 3.13   Electron density over time in 28 nm FDSOI transistor when Li = 12 nm and θ = 75° (ΦM = 4.52 eV, Wg = 100 nm).

Electron density over time in 28 nm FDSOI high-K transistor when Li = 24 nm and θ = 75° (Φ

Figure 3.14   Electron density over time in 28 nm FDSOI high-K transistor when Li = 24 nm and θ = 75° (ΦM = 4.52 eV, Wg = 100 nm).

LDD region and heavy-ion funnelling. (a) 32 nm bulk (Li = 30 nm, θ = 30°). (b) 28 nm FDSOI (Li = 12 nm, θ = 75°).

Figure 3.15   LDD region and heavy-ion funnelling. (a) 32 nm bulk (Li = 30 nm, θ = 30°). (b) 28 nm FDSOI (Li = 12 nm, θ = 75°).

Simulations were also performed using different metal-gate work function ΦM values in all transistors. Also, in the FDSOI cases, simulations were performed using devices with different gate equivalent oxide thickness tEOX. The materials of the polymeric metal gate of the devices and the gate oxide thickness have influence on CC. The CC is formed by mobile charges generated when the heavy-ion funnels through the device, and the charge of the depletion zone Qd. The charge Qd depends on the ΦM and gate oxide capacitance Cox = ɛEOX/tEOX:

3.7 Q d C ox ( Vth Φ M + Φ S + q ( N tox / C ox ) 2 φ F )

where ΦS is the body/channel semiconductor work function, q = 1.602 × 10−19 C is the electron charge, Ntox is the total oxide charge surface density and ϕF is the silicon Fermi potential. So, increasing ΦM and tEOX decreases Qd, and also decreases the total SET CCs (Calienes et al., 2015). If tEOX decreases, the device is predisposed to produce more CC due to a heavy-ion impact. The CC can be modelled as the sum of Qd and the mobile charges produced by the heavy-ion impact. Figure 3.16 presents a comparison between two 28 nm FDSOI transistors (tox = 0.9 nm) with different ΦM: 4.25 and 4.52 eV (these data are used to obtain the data of Figure 3.10). The heavy ion has the same LET = 100 MeV-cm2/mg and characteristics as in the previous simulations. The simulated impacts occur in two Li locations: 12 and 30 nm. Therefore, the transistor with ΦM = 4.25 eV collects more charge due to a heavy-ion impact than the ΦM = 4.52 eV one in a linear proportional relation, almost as predicted in Equation 3.7. This relation is no longer valid when the ion funnels through the drain, the LDD region and the body/channel at the same time. Figure 3.16 shows what happens in this case, when θ = 60° and Li = 12 nm: the CC in the ΦM = 4.52 eV case is greater than when ΦM = 4.25 eV.

Comparison between two 28 nm FDSOI transistors with different Φ

Figure 3.16   Comparison between two 28 nm FDSOI transistors with different ΦM and two different drain impact locations Li.

The drain terminal is the most sensitive area in these devices, because in all cases, the heavy-ion impact on this terminal produces more CC than the impact on the source terminal. In this case, Vds = Vdb = 1 V is the voltage at the drain terminal and Vsb = 0 V is the voltage between the source and substrate terminals. In this case, the drain-body n-p junction is reverse biased (Vdb = 1 V and the quasi-Fermi levels of the drain and body are different) and there is a large depletion region with a lot of depletion charge. In the source-body n-p junction case, the depletion region is thin due to the very low-voltage difference (in this case, Vsb = 0 V and the quasi-Fermi levels are almost the same). These depletion charges increase the total CC when the ion funnels through the device. In the bulk transistor, it is possible to have almost the same CC if the ion impacts both terminals with an angle θ > 45°, because there is the possibility to funnel into the LDD region from both the drain and source impact locations. In the bulk transistor, the channel region has a relativity high doping, and this increases the final SET CC. For the FDSOI devices, the low-doped channel region has a low charge contribution to CC after a heavy-ion impact. This fact, combined with the thin body/channel region and the bigger BOX region below the body/channel in the FDSOI transistor, would necessitate a very sharp angle (θ > 70°) for the ion to funnel through the LDD region and to obtain almost the same CC as having a heavy-ion impact on the source or drain terminals.

The BP and BOX in the FDSOI devices have advantages in a radiation environment. When the heavy-ion funnels through the device, the charges do not return to the channel, because the BOX isolates the charges, avoiding a contribution to the drain current. The grounded BP discharges the transistor substrate slowly (Calienes et al., 2015).

3.5  Heavy-Ion Impact Simulation on 6T Static RAM Cells

In order to simulate the effect of a heavy-ion impact on a six-transistor SRAM (6T SRAM) in these three devices, with the goal of comparing the radiation effects, it is necessary to create and set up the circuits for the test. The objective is to see what happens with the data stored in the cell and what is the minimum particle LET and CC to produce an SEU. The simulated memory cell schematic is shown in Figure 3.17 (Calienes et al., 2014). The cell is in retention mode with a supply voltage of 1 V, the word line (WL) is at 0 V and the bit lines (BL and BL) have 0 A current supply sources, to simulate high impedance. In this case, the TCAD simulation was performed in mixed mode; that is, five transistors were described using a SPICE model card and the impacted transistor was described at the device level. Tables 3.3 and 3.4 present the dimensions of each transistor in the three test circuits. The mnl transistor is the one suffering a heavy-ion impact in the drain terminal in the worst-case CC for each device type. Transistors mnl and mnr have a bigger area than the other ones in this circuit. To simulate a logical 1 in the cell, the mnl drain (the OUTL node) is initialised at 1 V, while the mnr drain (the OUTR node) is initialised at 0 V. The BPs of the 28 nm FDSOI and 28 nm high-K FDSOI cells are tied to ground.

Mixed-mode 6T SRAM cell. (From Calienes, W., et al., Impact of SEU on bulk and FDSOI CMOS SRAM, presented at Proceedings of 10th Workshop of the Thematic Network on Silicon-on-Insulator Technology, Devices and Circuits, Tarragona, Spain, January 29, 2014.)

Figure 3.17   Mixed-mode 6T SRAM cell. (From Calienes, W., et al., Impact of SEU on bulk and FDSOI CMOS SRAM, presented at Proceedings of 10th Workshop of the Thematic Network on Silicon-on-Insulator Technology, Devices and Circuits, Tarragona, Spain, January 29, 2014.)

Table 3.3   Transistor Dimensions of 32 nm Bulk 6T SRAM Cell

Transistor

Transistor Width W (nm)

Terminal Perimeter P (nm)

Terminal Area A (nm2)

W/L

mnal

160

560

19,200

5

mnar

160

560

19,200

5

mnr

217

674

26,040

6.78

mpr

91

422

10,920

2.84

mnl

217

674

26,040

6.72

mpl

91

422

10,920

2.84

Table 3.4   Transistor Dimensions of 28 nm FDSOI and 28 nm High-K FDSOI Memory Cells

Transistor

Transistor Width W (nm)

Terminal Perimeter P (nm)

Terminal Area A (nm2)

W/L

mnal

140

520

16,800

5

mnar

140

520

16,800

5

mnr

190

620

22,800

6.79

mpr

80

400

9,600

2.86

mnl

190

620

22,800

6.79

mpl

80

400

9,600

2.86

The total simulation time in all cases is Ts = 1 ns, and the heavy-ion impact occurs at ti = 0.490 ns. The LET is variable. The Li and θ values are chosen from the previous device simulations to obtain the maximum CC.

3.5.1  Simulation Results of 32 nm Bulk 6T SRAM

Heavy ions with 1–10 MeV-cm2/mg LETs were used to strike the drain terminal at Li = 30 nm and θ = 30° (the most disruptive condition for heavy-ion impact when the transistor is off state). Figure 3.18 shows the behaviour of the CC in the transistor mnl with different LETs. In these simulations, the minimum LET to flip the memory cell is 5 MeV-cm2/mg, and it produced 1.91 fC of CC, but the minimum CC to flip the cell (the ‘critical charge’) for this circuit was Cch = 1.76 fC. Using this Cch (Figure 3.18), the minimum estimated LET to flip the memory cell is approximately 4.75 MeV-cm2/mg. The grey area in Figure 3.18 is the critical area where the memory cell has a bit flip.

CC vs. LET characteristics of 32 nm bulk 6T SRAM cell (L

Figure 3.18   CC vs. LET characteristics of 32 nm bulk 6T SRAM cell (Li = 30 nm, θ = 30°). The grey area is the critical area when the cell flips.

3.5.2  Simulation Results of 28 nm FDSOI 6T SRAM

In this case, heavy ions with 60–70 MeV-cm2/mg LETs were used to impact the mnl transistor drain terminal at Li = 12 nm and θ = 75° (the worst case for this device in previous simulations). Figure 3.19 presents the results of the simulations for this memory cell. The grey area represents the critical area for the circuit. In the simulations, the cell flipped with LET = 64 MeV-cm2/mg and produced 2.03 fC of CC, but the Cch in this case was 1.78 fC when LET = 70 MeV-cm2/mg. The estimated LET to produce the Cch was approximately 63.6 MeV-cm2/mg, but it is possible to improve this result with more simulations using LET up to 90 MeV-cm2/mg. Figure 3.20 presents the voltage variation in the OUTL and OUTR nodes when a 64 MeV-cm2/mg heavy-ion impacts the mnl transistor drain terminal at Li = 12 nm and θ = 75°.

3.5.3  Simulation Results of 28 nm FDSOI High-K 6T SRAM

In this simulation, the heavy-ion impacts on the mnl transistor were performed using 45–55 MeV-cm2/mg LETs. The drain terminal was hit at Li = 24 nm and θ = 75°. Figure 3.21 shows the simulation results. The critical area for the circuit is shaded in grey. The minimum LET when the memory cell flipped was 50 MeV-cm2/mg, and it produced a CC of 1.89 fC. The critical charge is approximately Cch = 1.80 fC when LET = 55 MeV-cm2/mg. LET = 49.7 MeV-cm2/mg is the minimum estimated LET to generate this approximate Cch.

CC vs. LET characteristics of 28 nm FDSOI 6T SRAM cell (L

Figure 3.19   CC vs. LET characteristics of 28 nm FDSOI 6T SRAM cell (Li = 12 nm, θ = 75°). The grey area is the critical area when the cell flips.

OUTL and OUTR nodes voltages when a 64 MeV-cm

Figure 3.20   OUTL and OUTR nodes voltages when a 64 MeV-cm2/mg heavy-ion impacts the mnl transistor drain terminal in a 28 nm FDSOI memory cell.

3.5.4  Conclusions Related to the Heavy-Ion Impact Simulation on 6T Static RAM Cells

The flipping of a memory cell depends on the LET of the particle and the impact location in the transistor. In this case, to study the radiation effects, only impacts on the large NMOS transistors mnl and mnr were considered, but this methodology is also valid in the case of p-type MOSFET (PMOS) transistors, when the memory cell is in retention mode. All measurements were done using the most critical locations and angles, that is, where the device is more susceptible to produce more CCs.

CC vs. LET characteristics of 28 nm FDSOI high-K 6T SRAM cell (L

Figure 3.21   CC vs. LET characteristics of 28 nm FDSOI high-K 6T SRAM cell (Li = 24 nm, θ = 75°). The grey area is the critical area when the cell flips.

The 28 nm FDSOI memory cell is more resilient against heavy-ion impacts than the 32 nm bulk and 28 nm FDSOI high-K ones. The comparison of transient current pulses due to the heavy-ion impact, considering the worst cases for each cell, is shown in Figure 3.22. Table 3.5 shows the comparison among these cases. The 28 nm FDSOI cell is (in LET terms) 12.8 times more resilient than the 32 nm bulk cell, and 1.28 times more resilient than the 28 nm FDSOI high-K cell. In the three cases, the CC that flips a cell is almost the same, nearly 2 fC. The estimated critical charge Cch is almost the same in the three cases: 1.78 fC. A CC ≥ Cch is needed to flip these memory cells. Therefore, almost the same Cch needs to be generated to flip a cell in the three cases.

Figure 3.23 shows the electron density distribution as a function of time in the impacted transistor, in a 28 nm FDSOI high-K memory cell. A 50 MeV-cm2/mg heavy-ion impacts the drain terminal at TS = ti = 0.5 ns. The ion produces CCs, and a transient current pulse is generated as shown in Figure 3.22, and the cell is flipped. The probability of the generation of a current pulse also depends on how the transistors are connected in the circuit and on the circuit layout. When the ion impacts the mnl transistor drain terminal, the device is turned on briefly due to the charges produced by the impact; this voltage-level change in OUTL is sufficient to set in motion a positive feedback and flip the right-side inverter. This inverter changes its output OUTR value to an effective ‘high level’ and turns on the mnl transistor (last picture of Figure 3.23).

mnl transistor drain current for each simulated memory cell.

Figure 3.22   mnl transistor drain current for each simulated memory cell.

Table 3.5   Comparison of the Studied Devices in a 6T SRAM

Memory Cell Type

LET (MeV-cm2/mg)

CC (fC)

Cch (fC)

Maximum Pulse Amplitude (μA)

32 nm bulk

5

1.91

1.76

218

28 nm FDSOI

64

2.03

1.78

290

28 nm FDSOI high-K

50

1.90

1.80

321

The difference of the minimum LET to flip the 32 nm bulk memory cell and the 28 nm FDSOI memory cells can be explained by the difference in silicon volume of the affected device in each memory cell. The generated CC in the silicon is directly proportional to the LET times the distance travelled by the particle (Calienes et al., 2014).

The difference of minimum LETs between the 28 nm FDSOI memory cell and the 28 nm FDSOI high-K memory cell has another explanation. When the equivalent oxide thickness tEOX is thinner, the Cox is greater, and the depleted charge Qd is directly proportional to Cox, as shown in Equation 3.7. In the 28 nm FDSOI, tox = 0.9 nm, and this is the minimum silicon oxide thickness to avoid the gate tunnel effect. In the 28 nm FDSOI high-K, tox = tEOX = 0.75 nm for the polymeric HfO2-SiO2 gate oxide. This silicon oxide thickness of the high-K cell avoids the gate tunnel effect because the total sum of the two oxide layers is 1.833 nm, which is greater than 0.9 nm. This is one of the reasons to choose high-K devices when the technology node is less than 90 nm.

Electron density time variation of 28 nm FDSOI high-K memory cell mnl transistor (L

Figure 3.23   Electron density time variation of 28 nm FDSOI high-K memory cell mnl transistor (Li = 24 nm, θ = 75°, LET = 50 MeV-cm2/mg).

3.6  Conclusions

The main conclusion is that a FDSOI CMOS transistor is more resilient to heavy-ion impacts than a bulk CMOS one. The volume of silicon in the active region and its doping are deciding characteristics in choosing this technology to cope with heavy-ion impacts. The BOX and BP regions avoid the back recombination in the channel region, depriving any drain current from the substrate charge. The CC with the FDSOI transistor was approximately 7.7 times less than with an identically sized bulk transistor in the worst case.

In all cases, the drain terminal was more sensitive to heavy-ion impacts than the source terminal. The CC depended on the depletion region thickness in the impacted terminal.

The SET CC in the tested devices did not depend on the impact angle. The CC depended on silicon volume in the body/channel, the body/channel doping, the gate equivalent oxide thickness, the polymeric metal-gate work function, the source/drain contact diffusion geometry and the LDD location.

The 28 nm FDSOI memory cells were more resilient than the 32 nm bulk ones. It can be concluded that for the three types of cells, the same amount of charge needs to be generated in the silicon to flip the SRAM cells. FDSOI also has the advantage of using a much thinner layer in the body/channel region.

The 28 nm FDSOI memory cell was more resilient than the 28 nm FDSOI high-K one. To avoid the tunnel effect in the gate insulator, it is necessary to choose the high-K cell. An equivalent oxide with a thin thickness predisposes a device to collect more charges when a heavy-ion impacts the device.

References

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Calienes, W., Reis, R., Anghel, C., and Vladimirescu, A. 2014. Impact of SEU on bulk and FDSOI CMOS SRAM. Presented at Proceedings of 10th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits, Tarragona, Spain, January 29, 2014.
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