Soft Errors in Digital Circuits Subjected to Natural Radiation

Characterisation, Modelling and Simulation Issues

Authored by: Daniela Munteanu , Jean-Luc Autran

Semiconductor Devices in Harsh Conditions

Print publication date:  November  2016
Online publication date:  November  2016

Print ISBN: 9781498743808
eBook ISBN: 9781315368948
Adobe ISBN:

10.1201/9781315368948-3

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Abstract

As metal oxide semiconductor field-effect transistor (MOSFET) scales have reduced, the integrated circuit (IC) sensitivity to radiation coming from natural space or present in the terrestrial environment has been found to seriously evolve [1,2 and 3]. Nowadays, for ultrascaled devices, natural radiation is inducing one of the highest failure rates of all reliability concerns for devices and circuits in the area of nanoelectronics [2]. In particular, ultrascaled memory ICs have been found to be more sensitive to single-event upset (SEU) and digital devices more affected by digital single-event transients (DSETs). This sensitivity to single-event effects (SEEs) is a direct consequence of the reduction of device dimensions and spacing within circuit blocks combined with the reduction of supply voltage and node capacitance, resulting in a decrease of both the critical charge (i.e. the minimum amount of charge required to induce a bit flip) and the sensitive area (i.e. the minimum collection area inside which a given particle can deposit enough charge to induce a bit flip) [2,4].

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