Role of Diffusional Interfacial Sliding during Temperature Cycling and Electromigration-Induced Motion of Copper Through Silicon Via

Authored by: Lutz Meinshausen , Ming Liu , Indranath Dutta , Tae-Kyu Lee , Li Li

Semiconductor Devices in Harsh Conditions

Print publication date:  November  2016
Online publication date:  November  2016

Print ISBN: 9781498743808
eBook ISBN: 9781315368948
Adobe ISBN:

10.1201/9781315368948-11

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Abstract

Chip-on-chip (CoC) means to stack multiple chips vertically on top of each other. It enables the placement of integrated circuits and analogue devices like sensors in one package. Reducing the footprint and the R-C delay, CoC is of special interest for autonomous machines with an advanced sensor system to handle complex environments, like autonomous cars in heavy traffic. In addition, the integrated sensor systems have to have a long life cycle (20–30 years) under harsh environment conditions. CoC structures are based on Cu-filled through silicon vias (TSVs) that vertically connect the single chips with each other. Under harsh environment conditions, the TSVs are subjected to thermomechanical cycling during service. The difference in thermal expansion between Cu (16.4 ppm/K) and Si (2.5 ppm/K) leads to compressive and tensile stresses in the Cu and the surrounding Si matrix. Temperature cycling (TC) shows that the resulting relative expansion and shrinkage of the TSV compared with the Si matrix leads to cracks at the interfaces between the TSV and the lower and upper metal lines and at the TSV sidewalls [1,2]. In particular, cracks at the interfaces between the TSV and the metal lines increase the resistance of the TSV connection and alter the purpose of the three-dimensional packaging concept [1]. Furthermore, stresses in the Si matrix degrade the performance of front-end structures like proximate transistors [3].

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