Modeling and Performance Analysis of CNT-Based Through Silicon Vias

Authored by: Brajesh Kumar Kaushik , Vobulapuram Ramesh Kumar , Manoj Kumar Majumder , Arsalan Alam

Through Silicon Vias

Print publication date:  August  2016
Online publication date:  November  2016

Print ISBN: 9781498745529
eBook ISBN: 9781315368825
Adobe ISBN:

10.1201/9781315368825-5

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Abstract

During the recent past, several researchers [1] have designed the stacked integrated circuit (IC) layers on top of each other in order to integrate more devices on a single chip with improved performance. This advocated technique, known as three-dimensional (3D) die stacking, primarily results in higher transistor density, improved speed, lower power dissipation and area [2]. Traditionally, the connections were made through the multiple intellectual property cores on a single die (system on chip), multiple dies in a single package (multichip package), and multiple ICs on a printed circuit board [3]. Later on, system-in-package technology was introduced in which dies containing ICs are stacked vertically on a substrate. Another stacking technique is package on package that uses vertically stacked multiple packaged chips [4]. The latest development in this area is the 3D stacked IC using through silicon vias (TSVs), which employs a single package containing a vertical stack of naked dies and allows the die to be vertically interconnected with another die. TSVs are primarily referred to as a vertical electrical connection, or vertical interconnect access (via), that passes completely through a silicon wafer or a die. A TSV-based 3D IC offers various advantages in integrating a heterogeneous system onto a single platform as shown in Figure 4.1.

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