Through Silicon Vias: Materials, Properties, and Fabrication

Authored by: Brajesh Kumar Kaushik , Vobulapuram Ramesh Kumar , Manoj Kumar Majumder , Arsalan Alam

Through Silicon Vias

Print publication date:  August  2016
Online publication date:  November  2016

Print ISBN: 9781498745529
eBook ISBN: 9781315368825
Adobe ISBN:


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The importance of through silicon vias (TSVs) in the three-dimensional integrated circuit (3D IC) design has been discussed. The numerous advantages such as higher integration density, bandwidth, performance, and functionality obtained from 3D ICs would not have been possible without the application of TSVs. The performance of a 3D IC is primarily dependent on the choice of filler materials used in TSVs. Copper (Cu) is the most commonly used filler material in 3D TSVs. However, in recent years, Cu has faced certain challenges due to the fabrication limitations in achieving proper physical vapor deposition (PVD), seed layer deposition, and performance limitations due to electromigration and higher resistivity [1]. The resistivity can be attributed to the combined effects of scattering and the presence of highly diffusive barrier layer that increases the difficulty in obtaining a high aspect ratio via. Therefore, researchers are forced to find replacements to the Cu-based TSVs. Graphene-based materials such as carbon nanotubes (CNTs) and graphene nanoribbons (GNRs) have emerged as an interesting choice of filler materials due to their lower thermal expansion, Joule heating, and electromigration. Moreover, their higher current- carrying capability, long ballistic transport length, higher thermal conductivity, and mechanical strength provide exciting prospects for their application as filler materials in TSVs. Keeping in view the extraordinary properties demonstrated by graphene-based materials, it is believed that the ICs will soon contain graphene-based filler materials in TSVs in order to carry forward the “More-than-Moore” technologies.

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