Three-Dimensional Technology and Packaging Techniques

Authored by: Brajesh Kumar Kaushik , Vobulapuram Ramesh Kumar , Manoj Kumar Majumder , Arsalan Alam

Through Silicon Vias

Print publication date:  August  2016
Online publication date:  November  2016

Print ISBN: 9781498745529
eBook ISBN: 9781315368825
Adobe ISBN:

10.1201/9781315368825-2

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Abstract

A new set of solutions is clearly required for the packaging technology to keep up the demand for high integration and low power consumption. Chip stacking has arguably emerged as the technology that caters to the need of both the advanced packaging techniques and the technology scaling. Numerous innovative designs of chip stacking have been proposed, and some of them have successfully been implemented for commercial purposes for many years. However, in the past, other techniques have been implemented to connect the stack chips. Some of these techniques are wire bonding, ball grid arrays (BGAs) or flip chip bumps, wafer-level packaging (WLP) of chips, and so on. All these techniques were able to provide improved functionality in a single package and were successful in replacing the earlier printed circuit board (PCB) connections. Additionally, stacking packaging techniques provide better electrical connectivity leading to reduce power consumptions and improve reliability of the system [1].

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