Enhanced Technology Integration for NVM

Authored by: Arup Bhattacharyya

Silicon Based Unified Memory Devices and Technology

Print publication date:  June  2017
Online publication date:  July  2017

Print ISBN: 9781138032712
eBook ISBN: 9781315206868
Adobe ISBN:

10.1201/9781315206868-16

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Abstract

With the ever-increasing application base, silicon based microelectronics and nanoelectronics technology and products have assumed an indispensable role in virtually every human activity. As a result, continued evolution is being sought in cost reduction, power reduction and enhancements in functionality, and performance and reliability of memory and logic products as well as integrated solutions such as SOCs. Toward such goals, small and large system solutions are being addressed with appropriate architecture in considering memory hierarchies limited to SRAM for performance and endurance, and NVMs for cost, functions, system speed, and reliability, ideally displacing other memory options and integrating both logic and memory in chip-level (SOC) or in package level (e.g., System-in-Package or SIP). This approach is likely to continue especially with the potential evolution of advanced planar and 3D NVM multifunctional devices and SUMs. In this chapter, we will first provide a brief overview of system-level integration of memory and logic technology followed by enhanced NVM device-technology integration schemes in greater detail.

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