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Band Engineering for NVM Devices

Authored by: Arup Bhattacharyya

Silicon Based Unified Memory Devices and Technology

Print publication date:  June  2017
Online publication date:  July  2017

Print ISBN: 9781138032712
eBook ISBN: 9781315206868
Adobe ISBN:

10.1201/9781315206868-15

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Abstract

High K dielectric films and gate–insulator work function control had been successfully solving the scaling issues of FET devices since the turn of the century. Gate stack for a silicon based NVM device is significantly more complex when compared to the gate stack design of an FET device and consists of multiple dielectric layers and interfaces. These interfaces and dielectric layers have unique roles in regulating carrier transport and storage in order to achieve the unique NVM properties of memory window, charge retention, and endurance as well as material integrity and device reliability. Electronic transport and storage is fundamentally quantum mechanical and band properties of solids play a pivotal role. This chapter highlights the role of band engineering to enhance extendibility and unique device properties of scaled NVM devices in the context of multilayered gate stack designs for the NVM devices.

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