Voltage Scalability

Authored by: Arup Bhattacharyya

Silicon Based Unified Memory Devices and Technology

Print publication date:  June  2017
Online publication date:  July  2017

Print ISBN: 9781138032712
eBook ISBN: 9781315206868
Adobe ISBN:

10.1201/9781315206868-13

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Abstract

Chapter Outline

Silicon based NVM devices are FET based. FET devices are being progressively scaled both horizontally, known as “feature-size” scaling as lithography is scaled, as well as vertically, with reduction in gate stack thickness which is intimately tied with power-supply voltage scaling and associated scaling of power requirements. Similar to the FET devices, NVM devices could not only be scaled in feature size, but also in gate stack EOT to enhance operability at reduced power. The reduction in gate stack EOT for NVM device is referred to as “voltage scaling,” with the implication of programming (writing and erasing) at lower voltage level and consequently at reduced power. For NVM devices, voltage scalability is, therefore, an integral element in NVM device extendibility. This chapter outlines the voltage scalability challenges for the silicon based NVM devices.

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