Conventional NVM Challenges

Authored by: Arup Bhattacharyya

Silicon Based Unified Memory Devices and Technology

Print publication date:  June  2017
Online publication date:  July  2017

Print ISBN: 9781138032712
eBook ISBN: 9781315206868
Adobe ISBN:

10.1201/9781315206868-11

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Abstract

Conventional silicon based NVM devices, technology, and products had an impressive history of evolution over the decades since their inception. These devices followed the evolution of silicon based FET technology and in particular the CMOS technology. As the feature size of silicon technology nodes scaled, the NAND FG NVMs as well as the NROM NVMs were effectively scaled. The success of these devices and related products broadened the application base for the nonvolatile memories. Such a scaling of conventional NVMs continued since inception, from 3 to 5 µm technology node down to 120–150 nm technology nodes until early twenty-first century [1]. In addition, significant advancement in overall technology integration, channel profiling, and STI scaling was achieved by this time frame [2,3]. This resulted in NAND-SLC cell implementations in the range of nearly 5 F2 cells [46] and NOR/NROM cell implementations of nearly 10F×F cells for embedded applications [7,8]. During years 2000 and 2001, NAND products achieved 1 Gb density (Chapter 8: [4,5]) while 32 Mb embedded NOR arrays were reported [8]. In spite of such an outstanding progress, many scaling challenges remained to be addressed. These challenges will be briefly mentioned here and reviewed in detail in Part II of this book.

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