Three-Dimensional Integration Stacking Technologies for High-Volume Manufacturing by Use of Wafer-Level Oxide-Bonding Integration

Authored by: Spyridon Skordas , Katsuyuki Sakuma , Kevin Winstel , Chandrasekharan Kothandaraman

3D Integration in VLSI Circuits

Print publication date:  April  2018
Online publication date:  April  2018

Print ISBN: 9781138710399
eBook ISBN: 9781315200699
Adobe ISBN:


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In this chapter, we describe two key technologies for chip stacking, one achieved by use of die-level stacking and another based on wafer-level stacking, with the main emphasis on the wafer-level stacking technology. For the former, 3D die-level integration technology was developed using large-die 22 nm complementary metal oxide semiconductor (CMOS) technology, where die assembly was achieved on a laminate with seven layers of build-up circuitry on each core side. The design features integrated through-silicon vias (TSVs), microbumps, back-end-of-line (BEOL) wiring structures, and assembled controlled collapse chip connections (C4) joints, with Cu TSVs integrated in the BEOL. Void-free TSVs were formed, and the additional BEOL levels were fabricated after TSV processing and subsequently planarized by chemical–mechanical planarization (CMP). The types of bumps used to achieve interconnection were low solder volume with Cu pillars from the top die to the bottom die and high solder volume for the bottom die to the laminate with the package exhibiting reliable assembly process, high-quality connections, and very good thermal performance.

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