Wafer-Level Three-Dimensional Integration Using Bumpless Interconnects and Ultrathinning

Authored by: Takayuki Ohba

3D Integration in VLSI Circuits

Print publication date:  April  2018
Online publication date:  April  2018

Print ISBN: 9781138710399
eBook ISBN: 9781315200699
Adobe ISBN:

10.1201/9781315200699-5

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Abstract

Interest in packaging-based three-dimensional integration (3DI) technology using wafer-level processing has been increasing again. This is driven by the physical and economic limits of conventional scaling, which is no longer a main stream for the increasing demands for device performance, system form factor, and total manufacturing cost. This chapter discusses a back-end-of-line (BEOL)-compatible wafer-level 3DI approach including state-of-the-art interconnecting technologies such as bumpless vertical interconnects and ultrathinning of 300 mm wafers down to micrometer thickness.

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